This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. In addition, data from either of the digital audio interface channels can be routed to either the left or the right DAC. These register bits are described in Table The digital audio data is converted to oversampled bit streams in the on-chip, true bit digital interpolation filters.
The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. When enabled, this gradually attenuates the volume of the DAC output. This mono mix will be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. Only one DAC must be enabled in order to use this function. Normal bias x 0. Selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes WM The input signals to the speaker mixers are enabled and controlled using the register fields described in Table These mixers provide a selectable 0dB or -6dB volume control on each input.
The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions Table The analogue circuits in the WM require a bias current. Note that the normal bias current source requires VMID to be enabled also.
VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied.
The WM incorporates pop-suppression circuits which address these requirements. In these cases, the user does not need to set these register fields directly. WM The register bits relating to pop suppression control are defined in Table When enabled, the DC servo ensures that the DC level of these outputs remains within 1. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption An alternative method to apply known correction settings is to read the correction values from the WM register map and to store these for later use.
After DC offset correction has been performed, the applicable correction values can be read from the fields in the Servo Readback registers R81 to R84 described in Table LSB is 0.
Figure BCLK slave mode. All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. The WM can be programmed to send and receive data in one of two time slots. WM The register bits controlling audio data format and word length are summarised in Table The other bits up to the LSB are then transmitted in order.
Note: The WM is a bit device. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 47 to Figure This provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization WM The companded data is also inverted as recommended by the G. Companded data is transmitted in the first 8 MSBs of its respective data word, and consists of sign 1 bit , exponent 3 bits and mantissa 4 bits , as shown in Table MCLK itself is exact.
This may be input or output. The associated control fields are described in Table In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 7-bit device ID this is not the same as the 8-bit address of each register in the WM The default device ID for the WM is 0x34h.
It provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. Writing this bit aborts the current sequence and returns control of the device back to the serial control interface.
Writing this bit starts the write With this setting, 4-bit data would be written to bits and so on. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the need for read-modify-write procedures This is the memory location to which any updates to R and R will be copied RAM addresses Width of the data block written in this sequence step.
The purpose of these sequences, and the register write required to initiate them is summarised in Table In both cases a single register write will initiate the sequence Enhance your users' audio experience through Cirrus Logic's hardware and software solutions: Audio, Haptic, and Voice.
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